Monday, July 31, 2017

FPGA Design with High Level Synthesis (HLS), Our Online Course at

High Level Synthesis is Hardware (FPGA) Design Approach which provides design flexibility to Hardware and Software Engineer. Designer/Engineer can script their algorithm on C/C++ with HLS Tool (as VIVADO HLS, one add in application package with VIVADO) and Convert the C/C++ project in to HDL (Verilog/VHDL and System C).So HLS Design Tools gives extensive library support on Video/Image Processing, Computer Vision and Mathematical Computation.

FPGA Design with High Level Synthesis at

Want to Learn more on HLS Design Methodology, Designing, Synthesizing, Simulating and Implementing (Exporting) HLS design then take the Udemy Course on : FPGA Design with VIVADO HLS, We have provided the's course coupon with this link so you can take this course at $9.99. or Coupon Code Link .

In the Course we have provided free preview session on VIVADO HLS Overview and Design Flow of HLS on FPGA Design. So Join the course and Get idea of HLS.

Sunday, July 23, 2017

Summary of Second All Nepal FPGA Design Competition July 15, 2017

Digitronix Nepal had Organized Second All Nepal FPGA Design Competition 2017 with Co-Organizers of Kathford Int'l College of Engineering and Management, National College of Engineering, Sagarmatha Engineering College and Kathmandu Engineering College.
The Second Edition of FPGA (Field Programmable Gate Array, a hardware design platform) has explore the different new ideas, research capability and development in Nepal. The Main Attraction of the Competition is AES (Advance Encryption Standard) Encryption of the data for communication, Face Recognition with PYNQ (Python+Zynq) FPGA, Image Annotation (recognition and labeling) with Zynq FPGA, OFDM (Orthogonal Frequency Division Multiplexing, an optimized FDM) implementation on FPGA, Voting Machine Design with FPGA. Judge and Visitors of the competition also heavily interested on Spectrum Analyzer with FPGA, Digital Clock with Spartan 3E, PS2 Keyboard and LCD interfacing with FPGA and LCD interfacing with FPGA.
This Edition of FPGA competition make a new direction on FPGA Research and Development in Nepal. Digitronix Nepal is partnering with National and International Companies/Organizations for manufacturing some of this feasible ideas and marketing on the global market.
Digitronix Nepal is hopeful that more and more stakeholders of the Hardware Design Ecosystem will join the “Hardware Research and Development Initiative in Nepal” for creating more and more opportunities for Nepalese Engineering professionals.

Friday, July 21, 2017

Tutorial on Configuring Flash PROM and SPI PROM with Spartan 3E

Digitronix Nepal has prepared Tutorial on :
  1. How to Create and Program Flash PROM XCf04s on Spartan 3E
     2. How to Program SPI PROM of Spartan 3E Tutorial by Rukesh Prajapati (Winner of Second All          Nepal FPGA Design Competition 2017) for Digitronix Nepal.
If you need this Tutorials on Spartan 3E FPGA then you can contact us at : This tutorial has been referenced from Xilinx UG230 for Spartan 3E.

Sunday, July 16, 2017

Second All Nepal FPGA Design Competition 2017 Completed Successfully

Lots of Congratulations to Khwopa Engineering College - KhEC
Team Rukesh Prajapati of "AES Encryption of data for secure wireless communication" for winning the Second All Nepal FPGA Design Competition 2017, Lots of Congratulations to TU, IOE, Thapathali Campus team Ashutosh Karna, Sushma Pokharel, Aayush Shah of "Voting Machine Design" for winning First Runner Up Prize and Lots of Congratulations to Nepal Engineering College team Rajan Kanu Baniya, Abhidan Jung Thapa of "Implementation of OFDM Transmitter in FPGA" for Winning Second Runner Up Prizes of the Competition.
We would like to congratulate all the Nine participant teams for competing on the National Level FPGA Competition.
We would like to thank Kathford International College of Engineering and ManagementNational College of Engineering (NCE)Sagarmatha Engineering College and Kathmandu Engineering College for Co-organizing/Sponsoring the competition.
We are thankful to our Chief Guest Dr. Surendra Shrestha (Reader, IOE Pulchowk Campus) for being with todays competition as Chief Guest.
We would like to thank our Jury Members Subodh Ghimire sir (Asst. Prof. KU, SOE), Dinesh Baniya Kshatri sir (DHOD, ECE , IOE Pulchowk) and Raju Shrestha sir (Lecturer, National College of Engineering - NCE)
We are thankful to Dr.मधुसुदन कायस्थ sir, Principal of Kathford International College of Engineering and Management and Saban Kumar KC Coordinator of Kathford Research & Development- R&D.
We are thankful to Shakya Deepesh Sir for inspiration and motivation for FPGA Research and Development in Nepal. Deepesh Sir's support and effort make this level on FPGA R & D in Nepal.

Friday, July 14, 2017