Wednesday, April 27, 2022

LogicTronix ANPR Solution available for Asia Pacific and North America

LogicTronix is offering AI-enabled "Smart Parking" solution for private parking , public parking, multi-storey parking and toll booth management. LogicTronix ANPR is AI optimized solution based on "Cost Per Stream (CPS)", it is low cost, plug and play solution which can be deployed with Xilinx MPSoC Kria KV260, Kria SoM, Ultra96v2 , custom MPSoC SoM and other edge based platforms. LogicTronix ANPR solution supports, RTSP or IP Camera, USB , MIPI and IAS Camera sensors.

LogicTronix ANPR supports "Vehicle License Plates" of Thailand, Malaysia, Japan, India, where "English (Embossed/Non-Embossed) and Regional Character" based license plates are deployed.

Video Demo of LogicTronix ANPR Solution with Xilinx Kria KV260:

Features of LogicTronix ANPR Solutions

  1. LogicTronix ANPR is complete Edge based solution and also have cloud based feature!
  2. Developed with Xilinx MPSoC [EV / EG Series] FPGA platform, works with Xilinx Kria SoM, and multi-vendor SoMs on Xilinx MPSoC,
  3. GUI Functionality for easy User Interface,
  4. Work for standard number plates as well as number plates in regional language!
  5. Can took multiple RTSP/IP-camera streams (4 or upto 8) depending on the configuration and requirement,
  6. Ready to deploy and plug-and-play solution,
  7. Customers can get timely Solution-Update with “Additional Features” on request, remote feature update functionality.



For any queries and evaluation of LogicTronix-ANPR, please write at: info@logictronix.com.

Sunday, October 31, 2021

Winner Announcement of "2nd International FPGA Design Competition"!

We have announced the winner of the "2nd International FPGA Design Competition 2021"!  

Here are the team and project title of the winning projects:

  • Winning Project: Open SOC by Srimanth Tenneti from CVR College of Engineering, India. 
  • Runner-Up Project: GbHdmi by Fabien Marteau from FPGA Liberation Front, France. 

We like to congratulate Winner and Runner-Up of the competition. Here is the all details of the winning projects and the all Finalist of the competition!

We also like to congratulate all competent/participant who went up-to final! We and LogicTronix [FPGA Design & Machine Learning Company] are thankful to all Participant, Jury, Supporter and Sponsor for this edition of FPGA Design Competition! 

Wednesday, September 15, 2021

2nd International FPGA Design Competition 2021

We are announcing "2nd International FPGA Design Competition 2021"! In collaboration with LogicTronix , we are announcing 2nd edition of "International FPGA Design Competition". In this competition, participant from Any Country, with Any FPGA board/tools and/or with simulation based design can participate!

Here are the Timelines:
1.Registration : September 5 - October 20, 2021
2.Project-Progress-Demo [virtual] : October 25-27, 2021
3.Final Demo & Winner Announcement [virtual]: Sunday, October 31st, 2021
Know about 1st "International FPGA Design Competition-2019": https://lnkd.in/eBMAJKnV or visit: https://lnkd.in/ehY-syHm
#FPGA #Design #Competition #2nd #Digitronix #Nepal #LogicTronix

Saturday, September 11, 2021

Winner Announcement of "6th National FPGA Design Competition 2021"!

The "Winning Project" of this 6th edition of "FPGA Design Competition" is "Implementation of Optimized Vedic Multiplication Core in Verilog & Xilinx Zynq FPGA" by Santosh Shaha of Kathmandu University, School of Engineering.

The "Best Project Idea" title goes to project "QPSK Modulation and Demodulation in FPGA for Wireless Communication" by team of Bikesh Dhonju, Rajal Baral, Sanuj Kumar Shah and Pramod Karki , Khwopa Engineering College - KhEC, Bhaktapur".
The Winning Project and Best Project Idea teams will get "Cash Prize, Certifications and Internship Offering" from us (Organizers). All the participants of the FPGA Design Competition will get "Certification of Participation"!
We are thankful to all sponsors , all the participants and judges of the competition! We are grateful to LogicTronix for being Co-organizer of this FPGA Design Competition.