Winner Announced - 9th National FPGA Design Competition 2026

Winner Announced!!!

Today, the final demo and evaluation of the 9th National FPGA Design Competition 2026 was held at the Nepal Engineers’ Association Building, Pulchowk.

Based on the final evaluation, the team “Particle Path Tracking using GNN on FPGA” from IOE Pulchowk Campus emerged as the winner, while the team “Weather Parameters Forecasting using FINN with PYNQ FPGA” from Kathmandu University secured the runner-up position.

We extend our congratulations to all participating teams and commend their hard work and dedication in FPGA/VHDL/Verilog development, as well as system and accelerator design.

We are thankful to Jury team, Staff FPGA Design Engineer (LogicTronix Technologies) Abhidan Jung Thapa and Staff FPGA Design Engineer(LogicTronix Technologies) Nikil Thapa for their time for the judgement-hour. We are also grateful to Nepal Engineers Association (NEA) for providing venue for the competition final demo and winner announcement day.
#Nepal #FPGA #Design #Competition #Final #Semiconductor

 

(Please click on the image to see in high quality) 

 

The short detail about the participating project and team are at below: 

 

 

(Please click on the image to see in high quality) 

Venue of 9th National FPGA Design Competition 2026 - Final Demo

The 9th National FPGA Design Competition Finals will be held at Nepal Engineers' Association Building in Pulchowk, Lalitpur! Visitors are also warmly welcome.
We will be hosting the 9th National FPGA Design Competition 2026, including the final demonstrations and winner announcement, at the NEA Building, Pulchowk, Lalitpur.
We are thankful to Nepal Engineers Association for facilitating us!

See you there at January 24th! 

#FPGA #Competition #Semiconductor #Design #Nepal

9th National FPGA Design Competition 2026 - Nepal

We and LogicTronix Technologies are jointly announcing the 9th edition of FPGA Design competition in Nepal - "National FPGA Design Competition 2026".

This competition is opened theme competition for Nepali students and enthusiasts. 

 

The competents can register/compete with any project on FPGA with:

1. VHDL/Verilog, 
2. MATLAB/Simulink (System Generator or Model Compose or HDL coder) or 
3. IP design based projects 
4. Complete simulation or architecture based projects 
5. Projects targeted for Bitstream only or Baremetal or Linux based project.

Design with simulation based output or architectural output or the board test , any projects can register and compete.

 

Here is the timelines of the competition:

Registration : December 15th, 2025 – January 10th, 2026 
Project-Progress-Demo  : January 15th, 2026
Final Demo & Winner Announcement : Saturday, January 24th, 2026  (Magh 10 , 2082) 

 

Registration Form - https://forms.gle/nCHuz4JHe14tkfEq7   

Prizes + Certifications: 

• Winner of the competition will get Prize worth of NRs. 25000 and ,
• Runner-Up will get prize worth of NRs. 15000. 

Prize include Cash Prize + Internship + Courses , in-bundle along with certificates. 

Nepal Semiconductor Meetup 1.0

We , NSIA is organizing Nepal semiconductor meetup 2025 , a v1.0 event on semiconductor domain in Nepal. If you are interested on this event then please fill up the registration form.

Here is the event detail:

Date/Time - August 9th Saturday [12PM to 1:30PM]

Venue - LogicTronix Technologies, Kupondole, Lalitpur, Nepal

Google Map - https://maps.app.goo.gl/ifUybaT9cQCjgDTaA

Contact - info@logictronix.com or digitronixnepali@gmail.com

Phone - 9841078525

Agendas of Meetup:

1. Networking between Semiconductor Design professional or enthusiast in Nepal.
2. To share knowledge and ideas around semiconductor design - FPGA and VLSI design.
3. Open sourced and vendor specific resource and project idea discussion on semiconductor.
4. Community setup for "Nepal Semiconductor Development - Vision".
5. Sharing Vision, Mission and Goal of NSIA and roadmap ahead.

 Registration Form: https://forms.gle/JKRb3MtqdCsY5QXR8