Monday, July 16, 2018

Nepal Engineering College Student Win “3rd National FPGA Design Competition-2018”.

The “3rd National FPGA Design Competition 2018” has been concluded with the grand success today at Kathford Int’l College of Engineering and Management, Balkumari, Lalitpur. The competition was jointly organized by Kathford Int’l College of Engineering and Management, Digitronix Nepal Pvt. Ltd and LogicTronix.

The main objective of the competition is to promote electronic hardware design based on FPGA [An Reconfigurable Chip Technology] in Nepal. This Competition is the continuation of the “Second All Nepal FPGA Design Competition 2017” which was held on July 15, 2017 at Kathford Intl’ College of Engineering and Management and “First FPGA Design Competition 2016” held at July 2. 2016 at IOE Pulchowk Campus.

In the competition the total participant teams are 10, the winner of this contest is Arjun Neupane from Nepal Engineering College with project – “16-bit Microprocessor Design, Simulation and Implementation”, was awarded a cash prize of NRs. 15,000. The first runner-up, Ms. Shweta Chaudhary, Kala Raut and Ichchha Rauniyar from Khwopa Engineering Campus with the project traffic light design and prototype for Baneshowr Chowk, and the second runner-up, Mr. Subash Pandey from IOE Thapathali Campus with the project Vehicle Number Plate Recognition, received Rs. 7,000 and Rs. 4000 respectively. The award winners will also get an opportunity to receive training on Xilinx Zynq FPGA development board and Internship on FPGA research and development at Digitronix Nepal. The competition also get request from the international participant’s from Indian Institute of Technology (IIT)-India & some university students from USA, in the upcoming competition organizer will also include those international request for the participation on FPGA Design Competition.

An advisor of this event Mr. Deepesh Man Shakya, a Xilinx FPGA Engineer said this 3rd edition of FPGA Design Competition is a major milestone in introducing and enhancing FPGA education in Nepal and provide a platform for creating FPGA based research and development centers. Mr. Shakya said such initiatives could potentially turn into a design house providing hi-tech engineering jobs to many aspiring engineers within the country.

Dr. Madhusudan Kayastha , Principal of Kathford International College of Engineering and Management suggested to participant for preparing research papers and articles which will help then for further courier. The co-ordinator of this competition Mr. Krishna Gaihre from Digitronix Nepal & LogicTronix said that there has been a huge interest from engineering colleges and students towards FPGA Research and Development. Digitronix Nepal is currently focused on training, research and development of hardware designs based on FPGA. Digitronix Nepal also believes that within few years it will be create 10s of opportunities for Nepalese Engineering Graduates on the field of FPGA Design & VLSI Design.

The chief guest at the event Prof. Dr. Dinesh Kumar Sharma from IOE Pulchowk Campus lauded the event organizers and supporters for the effort they have put and also expressed his support in adopting FPGA in the mainstream engineering courses and help develop FPGA research environment in engineering colleges in Nepal.

Sunday, June 3, 2018

"3rd National FPGA Design Competition 2018" Timelines Released

The "3rd National FPGA Design Competition 2018" Timelines has been Released.

Learn, Explore, Compete and Win the National FPGA Design Competition!

Here we have the timelines:

Registration : May 20 –July 3, 2018
Project idea submission : July 3- July 6 , 2018
Project Progress submission : July 8, 2018
Pre Project Demonstration : July 11, 2018
Final Demonstration & Prize Distribution : Saturday, July 14, 2018 (Ashad 30,2075)

Competition Themes: Open (You can register and compete with any project idea on FPGA, Project only having Simulation Result will also eligible)
Past FPGA Competition at 2016 & 2017 Archives:
First National FPGA competition July 2, 2016, IOE Pulchowk Campus
Second All Nepal FPGA Design Competition July 15th 2017, Kathford College
For More Details, Please Contact: or

Tuesday, April 24, 2018

LogicTronix, the Digitronix Nepal Company on FPGA Design

LogicTronix, The FPGA Design Company of Digitronix Nepal has landed on the market with the expertise on Embedded Development, FPGA IP Development, Zynq 7000/Zynq Ultrascale+MPSoC Development, Real Time Video/Image Processing, Communication System Development, Computer Vision with Machine Learning and many more...
 For Further Services,Contact: or  Visit:

Tuesday, February 6, 2018

White Paper and Reference Guide from Digitronix Nepal on FPGA Design

Our Online Courses at Udemy, along with $9.99 Coupon Code Link:

  1. FPGA Design with VHDL: Online Course Session at Udemy: $9.99 Coupon Code
  2. FPGA Design with System Generator: Reference Documents and Online Course's Coupon of Udemy:$9.99 Coupon Code of Udemy Course
  3. FPGA Design with High Level Synthesis: Reference Document's and Online Course $9.99 Coupon Code
  4. Embedded System Design with Xilinx VIVADO and Zynq FPGA: $9.99 Coupon Code
  5. Verilog Programming with VIVADO Design Suit: $9.99 Coupon Code
  6. Verilog Programming with ISE Design Suit: $9.99 Coupon Code
  7. VHDL Programming with ISE Design Suit: $9.99 Coupon Code
  8. Zynq Ultrascale+MPSoC Development: $9.99 Coupon Code
  9. Zynq Development with SDSoC Tool: Free Course
Hot Course: Zynq Ultrascale+MPSoC Development Online Course at Udemy

Following are the white paper and reference guide on FPGA Design from Digitronix Nepal. If you need this resources then do send us Email at:

  1. Verilog/VHDL and Tcl Reference Guide
  2. PCIe Terminologies (from PCI to PCIe Gen 3): Whilte Paper
  3. White paper document on PCIe Gen4 new features and it's applications
  4. VIVADO Design suit Reference Guide
  5. Reference Guide on Xilinx's DMA Subsystem for PCIe: XDMA Example Design, Driver Installation, Debugging and Analysis Guide.
  6. lspci and setpci Reference Manual for Xilinx PCIe IP
  7. lspci and setpci scripts for automatic report generation and analysis
  8. Answer Record on Debugging at Device Startup (VIVADO ILA Trigger at Startup)
  9. Reference Guide: FPGA Design with OpenCL
  10. Reference Manual: Very High Speed Packet Processing System and Architecture: FPGA and Heterogeneous Computing Methodology
  11. Tcl Scripting for VIVADO Design's for automation and Design/Verification: Reference Guide
  12. AXI PCIe and MIG based design with Xilinx 7 Series, Ultrascale and Ultrascale+ FPGA's.