International FPGA Design Competition 2019-Winner Announced

Digitronix Nepal and LogicTronix has organized the "International FPGA Design Competition 2019", the winner and runner-up of the competition has been announced at August 210, 2019. Here are the Winner and Runner-up of "International FPGA Design Competition-2019".
Winner: 32-bit Harvard Microprocessor, Team: Ahmad Khaled , Hassan Ibrahim , Ahmad Tolan , Ahmad Ashour, University/Affilation: Cairo University - Faculty of Engineering, Country: Egypt

Runner-up: Design and Implementation of a Frequency Hopping System based on FPGA, Team: Ahmed M. Alfadhel, University: Al-Furat Al-Awsat Technical University, Country: Iraq

We would like to Congratulate to all winners and all participating teams!
#International #FPGA #Design #Competition #2019

Here is the details of all teams participating on the Competition.

"4th National FPGA Design Competition 2019" Concluded Successfully

"4th National FPGA Design Competition 2019" concluded today! Among the 11 competing teams, the Winner of the competition is project "Vehicle to Vehicle Communication using FPGA" of Nikhil Thapa, Devendra Patel, Kishan Shrestha & Swarnim Shrestha from Khwopa Engineering College - KhEC, first runner up is project "Frequency Control of Synchronous Generator using Fuzzy Logic" of Rajiv Bishwokarma, Bishal Bhetwal, Shayarrn Khatiwoda from Kathmandu University, Dhulikhel and Second Runner up is project "Voting Machine" of Binita Pariyar, Rasmila Thike, Sunmoon Tulsibakhya & Usha Dahal from Khwopa Engineering College - KhEC.
Congratulations to all the Winners and Participant's!
Digitronix Nepal is thankful to today's Chief Guest Surendra Shrestha, PhD (HoD, Department of Electronics and Computer, IoE Pulchowk Campus), Jury Members: Asst. Prof. Deepesh Prakash Guragain (Nepal Engineering College), Er. Dinesh Baniya Kshatri (Thapathali Campus).
We are grateful to Kathford International College of Engineering and Management for being the Organizer of the event and we are grateful to Asso. Prof. Dr. Mahesh Chandra Luitel (Principal, Kathford), Er. Prabin Kumar Jha (D-HoD, Department of Electronics and Computer, Kathford) and Faculty of Kathford- Saban Kumar KC, Pawan Khadka ,Kiran Bagale and team facilitate today's event. Thank you everyone for supporting us and "FPGA Research in Nepal" Initiative!

International FPGA Design Competition 2019

Along with "4th National FPGA Design Competition-2019", we are also hosting "Online Version" of separate "International FPGA Design Competition-2019". We already getting participant request for the "International FPGA Design Competition" from different Countries. Fill the registration form: bit.ly/FPGA_Competition_2019

For any queries: info@logictronix.com or digitronixnepali@gmail.com.

4th National FPGA Design Competition-2019

The timelines of 4th edition of FPGA Design Competition is released.The themes of competition is Open- enthusiast having any project on FPGA can get eligibility for the competition. Timelines [Revised] are

Registration : June 15- July 23, 2019
Pre-Project Demonstration : July 24-25, 2019
Final Demonstration & Prize Distribution: Saturday, July 27, 2019 (Shrawn 11,2076) Registration Form: https://forms.gle/XAyTSFA1FMo2Cgw48

Machine Learning with VCU1525 and Alveo

We just have released video tutorial session on "Machine Learning with VCU1525 and Alveo, High Performance Cloud Accelerator". In this session we are Implementing YoloV2 for Object Detection/Recognition on Cloud FPGA Accelerator.
#Nimbix #AWS #FPGA #VCU1525 #Alveo #Xilinx
https://www.youtube.com/watch?v=Pc-as5DMHJk. This implementation is done at Dec, 2018 by our team.

SDAccel Development for Xilinx Alveo FPGA

In this session we have showed up about "how to develop OpenCL application on SDAccel with Nimbix and how to implement that OpenCL application on Xilinx Alveo FPGA". https://www.youtube.com/watch?v=FCP0sN_HInw

Webinar on "Computer Vision" & "Complex VHDL/Verilog Development!

Digitronix Nepal and www.LogicTronix.com had conducted Second session of "Webinar Series on FPGA". In this session we have talked with "how to structure the complex VHDL/Verilog projects", "how to write keccak for 12Gh/s+ hash rate" and "how to write AES encryption/decryption code on VHDL/Verilog". Webinar Recorded Link: https://youtu.be/KhDuwXFadvw

Here is the first webinar series video recording of "Computer Vision and Machine Learning with FPGA": https://youtu.be/zmDoTLNY_Ew for more details about the webinar series, please visit: https://logictronix.com/webinars/.

Online Courses + White Paper from Digitronix Nepal & LogicTronix

Our Online Courses at Udemy.com, along with $9.99 Coupon Code Link:

1. Embedded System Design with Xilinx VIVADO and Zynq FPGA: $9.99 Coupon Code
2. FPGA Design with VHDL: Online Course Session at Udemy: $9.99 Coupon Code
3. FPGA Design with MATLAB & Simulink [System Generator]:$9.99 Coupon Code of Udemy Course
4. FPGA Design with High Level Synthesis:  $9.99 Coupon Code
5. Verilog Programming with VIVADO Design Suit: $9.99 Coupon Code
6. Verilog Programming with ISE Design Suit: $9.99 Coupon Code
7. VHDL Programming with ISE Design Suit: $9.99 Coupon Code
8. Zynq Ultrascale+MPSoC Development: $9.99 Coupon Code
9. Zynq Development with SDSoC Tool: $9.99 Course Coupon
10. PYNQ FPGA Development with Python Programming: $9.99 Coupon Code
11. Video Processing with FPGA & VIVADO, HLS & SDK : $9.99 Coupon Code

Democratizing FPGA Education all over the World initiative of Digitronix Nepal and LogicTronix.com

Following are the white paper and reference guide on FPGA Design from Digitronix Nepal. If you need this resources then do send us Email at: digitronixnepali@gmail.com or info@logictronix.com

1. Video Processing with FPGA, Object Tracking, Video Overlay, Face/Eye Recognition
2. PetaLinux Development for Custom Application
3. Computer Vision with FPGA
4. Verilog/VHDL and Tcl Reference Guide
5. PCIe Terminologies (from PCI to PCIe Gen 3): Whilte Paper
6. White paper document on PCIe Gen4 new features and it's applications
7. VIVADO Design suit Reference Guide
8. lspci and setpci Reference Manual for Xilinx PCIe IP, automatic report generation and analysis
9. Answer Record on Debugging at Device Startup (VIVADO ILA Trigger at Startup)
10. Reference Guide: FPGA Design with OpenCL
11. Reference Manual: Very High Speed Packet Processing System and Architecture: FPGA and Heterogeneous Computing Methodology
12. Tcl Scripting for VIVADO Design's for automation and Design/Verification: Reference Guide