Monday, January 15, 2018

FPGA Design with System Generator (Matlab/Simulink) & HDL Coder

We are working with Projects on "FPGA Design with System Generator (Matlab/Simulink) and HDL Coder". This Matlab/Simulink based FPGA Design Platform System Generator (so called Sys Gen) is useful for Designing  and Implementing Signal Processing Projects (Image Processing, Audio Processing etc.).Furthermore, System Generator is heavily preferred for Digital Signal Processing.

From the System Generator we can design, test and implement Matlab or Simulink based project's on FPGA. We can create RTL Netlist or Generate HDL from the System Generator (Matlab/Simulink) Project or can generate Bitstream file from the System Generator so we can upload project directly to FPGA.
Another Design Flow is we can Run Co-Simulation of System Generator projects with FPGA Board (which is as real time hardware based simulation). Or we can create bit file and dump on the FPGA board. This design flow supports large number of FPGA Boards form Xilinx and Intel/Altera, so there are many references on FPGA Design with System Generator.

For any projects on System Generator (Matlab/Simulink) or HDL Coder for FPGA Development, you can remember us. You can mail us your requirement at: digitronixnepali@gmail.com
FPGA Design with System Generator and HDL Coder
FIR Implementation on System Generator


Thursday, January 4, 2018

2017 Review of Digitronix Nepal

Summarizing 2017, we have following reviews:
  1. We create few more courses on FPGA, until the end of 2017 we have SIX Courses on Udemy.com. You can ger $10 Course Coupon or Lucky Free Coupon's for that send us request at digitronixnepali@gmail.com or facebook.com/DigitronixNepal
  2. We have Completed the Implementation of Canny Edge Detection in High Level Synthesis (VIVADO HLS), finally we generate IP (so called Intellectual Property) and Exported it to VIVADO IP integrator and combine with other blocks (DMA's, Processing System's and HDMI IP's). We have tested this project and obtained outstanding result in Zedboard and ZC702 FPGA's, this design can be migrated to other Zynq Families and Kintex/Vertex Families.
  3. We have Created Userguide on "lspci for FPGA's", this user guide consists of all the lspci bash commands which show you information of PCI or PCIe cards connected to your PC/Motherboard. Example: $lspci -vvv this command show you all the information of your PCI/PCIe devices and registers, status etc. You can tried out this command on any Linux PC.
  4. We have Created the lspci bash script for getting required information from the installed card (FPGA or other PCI card's). Our lspci script will give you result of "which status register is set and which are unset" for identification of your card's issues and problems.  We can deliver any type of such script for custom problem and solution, for that send mail at: digitronixnepali@gmail.com.
We will update more review of 2017 soon, let us know if you have any interest on our Services and Products.
Cheers!
Happy New Year 2018 (Belated)!!!

Friday, November 10, 2017

Would you like to Work on FPGA Design and Verification Industry???

Are you interested to work on State of Art FPGA Technology for Computer Vision, Machine Learning Project's? You will get to have competent and global Skill Set on FPGA Design with VHDL/Verilog, High Level Synthesis(HLS, C/C++ Design Approach for FPGA) & Python/OpenCV If you really have patience and appetite to get those skillset which you can market globally, then write a brief application(Including CV) to digitronixnepali@gmail.com. #Digitronix #Nepal #Engaging #New #Team

Monday, October 30, 2017

Digitronix Nepal's Services

Digitronix Nepal is working on FPGA Desgin, VLSI Design and Verification from past 5+ Years.We have expertise on FPGA Design, fast prototyping signal processing projects, IP design/migration and more.We are offering following services to our valuable clients.

  1. Intellectual Property(IP) Design for FPGA/ASIC and Verification
  2. Tcl Scripting for FPGA/ASIC/VLSI Projects
  3. Complete FPGA Design Plan with Xilinx Technology (Including VIVADO based High Level Synthesis,IP integration, Developing Software Application for ARM CPU and Implementing Algorithm's with SDSoC Tool of Xilinx) and Support for PCB Design/Fabrication.
  4. PCIe Solution Support for Xilinx and NWlogic PCIe IP for FPGA (7 Series and Ultrascale FPGA).
  5. VIVADO Version Control and IP migration.
  6. Offline and Online FPGA/ASIC/VLSI Design & Verification Training with following Xilinx Training Partner's Syllabus and Verification Methodologies planned with reference of Doulos.

XAPP1167 (Application Note: Vivado HLS, Reference-Xilinx) Support- Accelerating OpenCV Applications with Zynq-7000 All Programmable SoC using Vivado HLS Video Libraries.If you need to modify xapp1167 and test design on Zc702 FPGA then can provide service to you. For different version of VIVADO project (or Tcl Source) of xapp1167 contact us at: digitronixnepali@gmail.com.