IP protection for Semiconductor and Integrated Circuit (IC) layout designs in Nepal

 📢 A small but important milestone toward building a Semiconductor Design Industry in Nepal.
The Government of Nepal has released bill to facilitate Intellectual Property (IP) protection for Semiconductor and Integrated Circuit (IC) layout designs.
Inventors and companies can now register their semiconductor integrated circuit layout designs as intellectual property with the Department of Industry, IP Rights and Trademark Registrar's Office, providing legal protection for their semiconductor design innovations.

This marks a positive step toward establishing a stronger legal and innovation ecosystem for semiconductor design in Nepal.
📄 More details - https://www.newbusinessage.com/news/49255/nepal-proposes-first-ever-legal-protection-for-chip-layout-designs/ 

 
#Nepal #Semiconductor #Design #Industry

 

Nepal Semiconductor Design Meetup 1.1

We , NSIA is organizing Nepal semiconductor design meetup 2026 , a v1.1  event on semiconductor design in Nepal. If you are interested on this event then please fill up the registration form.

Here is the event detail:

Date/Time - May 30th , 2026 , Saturday [12PM to 2:30PM]

Venue - LogicTronix Technologies, Kupondole, Lalitpur, Nepal

Google Map - https://maps.app.goo.gl/ifUybaT9cQCjgDTaA

Contact - info@logictronix.com or digitronixnepali@gmail.com

Phone - 9841078525

Agendas of Meetup:

1. Networking between Semiconductor Design professional or enthusiast in Nepal.
2. To share knowledge and ideas around semiconductor design - FPGA and VLSI design.
3. Open sourced and vendor specific resource and project idea discussion on semiconductor.
4. Community setup for "Nepal Semiconductor Development - Vision".
5. NSIA activity towards Vision, Mission and Goal and roadmaps.

 

 Registration Form - https://forms.gle/xhaLyo9BixK74ktc9 

Venue of 9th National FPGA Design Competition 2026 - Final Demo

The 9th National FPGA Design Competition Finals will be held at Nepal Engineers' Association Building in Pulchowk, Lalitpur! Visitors are also warmly welcome.
We will be hosting the 9th National FPGA Design Competition 2026, including the final demonstrations and winner announcement, at the NEA Building, Pulchowk, Lalitpur.
We are thankful to Nepal Engineers Association for facilitating us!

See you there at January 24th! 

#FPGA #Competition #Semiconductor #Design #Nepal

9th National FPGA Design Competition 2026 - Nepal

We and LogicTronix Technologies are jointly announcing the 9th edition of FPGA Design competition in Nepal - "National FPGA Design Competition 2026".

This competition is opened theme competition for Nepali students and enthusiasts. 

 

The competents can register/compete with any project on FPGA with:

1. VHDL/Verilog, 
2. MATLAB/Simulink (System Generator or Model Compose or HDL coder) or 
3. IP design based projects 
4. Complete simulation or architecture based projects 
5. Projects targeted for Bitstream only or Baremetal or Linux based project.

Design with simulation based output or architectural output or the board test , any projects can register and compete.

 

Here is the timelines of the competition:

Registration : December 15th, 2025 – January 10th, 2026 
Project-Progress-Demo  : January 15th, 2026
Final Demo & Winner Announcement : Saturday, January 24th, 2026  (Magh 10 , 2082) 

 

Registration Form - https://forms.gle/nCHuz4JHe14tkfEq7   

Prizes + Certifications: 

• Winner of the competition will get Prize worth of NRs. 25000 and ,
• Runner-Up will get prize worth of NRs. 15000. 

Prize include Cash Prize + Internship + Courses , in-bundle along with certificates. 

Nepal Semiconductor Meetup 1.0

We , NSIA is organizing Nepal semiconductor meetup 2025 , a v1.0 event on semiconductor domain in Nepal. If you are interested on this event then please fill up the registration form.

Here is the event detail:

Date/Time - August 9th Saturday [12PM to 1:30PM]

Venue - LogicTronix Technologies, Kupondole, Lalitpur, Nepal

Google Map - https://maps.app.goo.gl/ifUybaT9cQCjgDTaA

Contact - info@logictronix.com or digitronixnepali@gmail.com

Phone - 9841078525

Agendas of Meetup:

1. Networking between Semiconductor Design professional or enthusiast in Nepal.
2. To share knowledge and ideas around semiconductor design - FPGA and VLSI design.
3. Open sourced and vendor specific resource and project idea discussion on semiconductor.
4. Community setup for "Nepal Semiconductor Development - Vision".
5. Sharing Vision, Mission and Goal of NSIA and roadmap ahead.

 Registration Form: https://forms.gle/JKRb3MtqdCsY5QXR8  

Nepal Semiconductor Industry Association - NSIA , an Inception

We along with LogicTronix (AMD Global Partner for FPGA Design and ML Acceleration) and few more semiconductor-focused companies H.Q in Nepal are working on "Nepal Semiconductor Industry Association" with the following Vision and Goal.

• Vision - Creating a high tech semiconductor design ecosystem in Nepal
• Goal - To establish a high-tech semiconductor ecosystem in Nepal by 2027 

We, the founding member of this association are already serving "top global semiconductor companies" around the World since around decade.

We are also closely working with Global EDA companies, Design houses, Fabless companies, Open-source tools companies and partner of this ecosystem to realize our Goal.

If you like to join this initiative then you can contact us or follow the NSIA social media (Facebook) handle: https://www.facebook.com/profile.php?id=61573712832764

8th National FPGA Design Competition 2024/2025 Announced!

We , LogicTronix and LOCUS 2025 (IOE Pulchowk Campus) are jointly organizing the "8th National FPGA Design Competition 2024/2025" !

For more details of the competition, please visit following poster or keep tuning LOCUS 2025 social media handles!

Advanced FPGA Design Elective -I Course at IOE , TU, Nepal

Institute of Engineering (IOE) has approved "Elective-I" Syllabus on "Advanced FPGA and Embedded Design (EX72506)" which includes advanced FPGA design topics , recent FPGA design methodologies, Verilog development, VLSI-CMOS design approaches in Semiconductor Industries and multiple Lab sessions on FPGA. The syllabus and course development was done by LogicTronix in collaboration with IOE, Pulchowk Campus, the syllabus was created by targeting real world application and industry requirement in this Semiconductor/chips era . This year BEI and BCT students of 7th Semester from Pulchowk Campus took the elective and did very well while learning with it and gaining skills/knowledge in it.

Next year students from all IoE Campuses and affiliated colleges can took this elective and open door towards FPGA, VLSI and Semiconductor design field.

If you like to go through the Syllabus of this elective then you can check IoE Syllabus booklet or write here or at email info@logictronix.com!
#FPGA #Elective #IOE #Nepal #Pulchowk #Electronics #Computer #Electrical #Engineering #CSE #Semiconductor #VLSI #UniversityIndustryCollaboration #University #Grant #Commission

Call for Proposal from B.E Students for Final Year or Research Projects- Grant Announcement

Collaborating with LogicTronix(AMD-Xilinx's Global Partner for FPGA Design + ML Acceleration), we, Digitronix Nepal, are pleased to announce the "Final Year Project/Research Project Grant" for B.E or equivalent undergrad Students in Nepal(from any University/College or Institution) who wish to pursue final year or academic project or research project on topic related to "FPGA Design , Computer Vision, Machine Learning and Acceleration". 

Under this Grant Plan, final year students can pursue their academic project as usual(as a regular Final Year Project) at their University or College while we provide them with independent grants. We will also coordinate with the respective University or Colleges from where the project applied and received a grant from us.

Here is the timeline for the Project Proposals:

Project Proposal Registration Timeline: May 15th 2023 to December 31, 2023

Selection Timeline(Selection Results Announcement): Monthly till December 31, 2023

 

Grant Amount:

1. For the Final Year Project (Ranging time of one or two Academic Semester) , we will provide Grant of NRs. 20,000 (Twenty Thousand) to the Selected Team for the Selected Final Year or Research Project.
   
2. The Project Grant will be provided in two installment, half of grant amount will be provided after official starting of project(officially from university/college and us) and remaining half of Grant at the completion of the project (after report and project submission to University and us).

Selection Criteria(Evaluation Method):

1. We will evaluate project proposal and project plan thoroughly from the project team member. We will select and award the Grant to the deserving project team based on their project plan (effort and time).
2. Our team will review proposal based on following criteria(topics)
• Detail Plan for the Implementation (work to be done),
• Uniqueness or innovation (What innovation did the project team is proposing on project proposal),
• Optimization Level and Planned approach on Implementation, how the implementation will be optimized to get better results than the readily available implementation or works.
  
• [Optional] Possibility of implementing the project on edge platform (low power and low cost hardware).

Objective of this Grant:

1. To enhance skills of Engineering Students of Electronics, Electrical, Computer and equivalent in the field of FPGA Design(Verilog/VHDL/RTL/HLS/IP Design Methodology and Systems Design with FPGAs), Embedded Design, Machine Learning(ML Implementations, Optimization and Acceleration), Computer Vision(Vision Algorithms , Methodologies and Implementation), Algorithmic Development, Signal Processing, Different types of Processor Architecture Design and Low Latency Design
   
2. Enrich the Industry-Academic Collaboration in Nepal. This program aim to enrich and strengthen Industry-Academic Collaboration, so the graduates from Universities can get the "Real World Skills" around FPGA Design and Machine Learning so that on graduation they can be ready for garbing the Opportunity at Industries(Technology Companies or Design Companies).
   
3. On completion of this Grant project, students will obtain industry grade skills on FPGA Design and Machine Learning and ready for Job Opportunity.

After Final Year Project or Research Project: Project team members will also get Paid Internship Offer from LogicTronix after completion of this Grant Period (Project Period).

 

For "Grant Guidelines and Registration" visit: here

 

For any queries regarding to this Research/Final Year Project Grant, please contact us at email: digitronixnepali@gmail.com or info@logictronix.com.

Winner Announcement of "2nd International FPGA Design Competition"!

We have announced the winner of the "2nd International FPGA Design Competition 2021"!  

Here are the team and project title of the winning projects:

• Winning Project: Open SOC by Srimanth Tenneti from CVR College of Engineering, India. 
• Runner-Up Project: GbHdmi by Fabien Marteau from FPGA Liberation Front, France. 

We like to congratulate Winner and Runner-Up of the competition. Here is the all details of the winning projects and the all Finalist of the competition!

We also like to congratulate all competent/participant who went up-to final! We and LogicTronix [FPGA Design & Machine Learning Company] are thankful to all Participant, Jury, Supporter and Sponsor for this edition of FPGA Design Competition! 

2nd International FPGA Design Competition 2021

We are announcing "2nd International FPGA Design Competition 2021"! In collaboration with LogicTronix , we are announcing 2nd edition of "International FPGA Design Competition". In this competition, participant from Any Country, with Any FPGA board/tools and/or with simulation based design can participate!

Here are the Timelines:

1.Registration : September 5 - October 20, 2021

2.Project-Progress-Demo [virtual] : October 25-27, 2021

3.Final Demo & Winner Announcement [virtual]: Sunday, October 31st, 2021

Registration Form: bit.ly/2ndFPGACompetition_Intl

Know about 1st "International FPGA Design Competition-2019": https://lnkd.in/eBMAJKnV or visit: https://lnkd.in/ehY-syHm

#FPGA #Design #Competition #2nd #Digitronix #Nepal #LogicTronix

Know more about the "2nd International FPGA Design Competition 2021" and know about "International FPGA Design Competition 2019".

Winner Announcement of "6th National FPGA Design Competition 2021"!

The "Winning Project" of this 6th edition of "FPGA Design Competition" is "Implementation of Optimized Vedic Multiplication Core in Verilog & Xilinx Zynq FPGA" by Santosh Shaha of Kathmandu University, School of Engineering.

The "Best Project Idea" title goes to project "QPSK Modulation and Demodulation in FPGA for Wireless Communication" by team of Bikesh Dhonju, Rajal Baral, Sanuj Kumar Shah and Pramod Karki , Khwopa Engineering College - KhEC, Bhaktapur".

The Winning Project and Best Project Idea teams will get "Cash Prize, Certifications and Internship Offering" from us (Organizers). All the participants of the FPGA Design Competition will get "Certification of Participation"!

We are thankful to all sponsors , all the participants and judges of the competition! We are grateful to LogicTronix for being Co-organizer of this FPGA Design Competition.

6th National FPGA Design Competition 2021

Digitronix Nepal and LogicTronix are announcing "6th National FPGA Design Competition 2021"! This is 6th Series of "FPGA Design Competition in Nepal"! We will also be releasing timeline details for "2nd International FPGA Design Competition" soon!

Here are the timelines of the "6th National FPGA Design Competition":

Registration : August 1 – September 1, 2021

Project-Progress-Demo : September 7, 2021

Final Demo & Winner Announcement : Saturday, September 11th, 2021 (Bhadra 26 , 2078)

Registration Link: bit.ly/6thFPGACompetition

Participant can compete on this competition with any project on "VHDL/Verilog/HLS/Python/OpenCL or FPGA Development or Machine Learning with FPGA or any topics on FPGA or architecture design or processor designs with FPGA"!

LogicTronix is "Xilinx Alliance Member" and "Design Service Partner" for AI/ML for Xilinx SoM

LogicTronix.com  is now "Xilinx Alliance Member" ! With the "Xilinx Alliance Membership", LogicTronix will have more reach on customers who use Xilinx FPGAs on their application. Details of Xilinx Alliance Member ship can be found at here [Alliance Membership-LogicTronix].

LogicTronix also now the "Design Service Partner" for Xilinx Kria System on Module (SoM) for "AI and Machine Learning Acceleration". This Kria family of MPSoC FPGA released at April 20th 2021 and SoM built on it are best suited for accelerating "advanced computer vision applications" including video analytics, smart camera, machine vision etc. LogicTronix already have developed some of the computer vision solutions on the KV260 kit and Kria K26 SoM, and they will be releasing those high performing solutions very soon! 

Details of Kria SoM: https://lnkd.in/ea83PYt. More about KV260: https://lnkd.in/ez2W9ek 

Xilinx SoM partner page [Link]

5th National FPGA Design Competition 2020 Concluded

We (organizers) have announced the winners of the "5th National FPGA Design Competition 2020"!

In this 5th edition of "FPGA Design Competition" we have "Winning Project" on "Video Encryption and Decryption with AES on FPGA" by project members Diwakar Kc, Akash Manandhar and Sagar Humagain from Khwopa Engineering College - KhEC. 

The "Best Project Idea" title goes to "PYNQ FPGA based face recognition and attendance system" project by Ishwor Shrestha and Pradipt Sharma from Kathmandu Engineering College. The Winning Project and Best Project Idea teams will get "Cash Prize, Certifications and Internship Offering" from us (Organizers). All the participants of the FPGA Design Competition will get  "Certification of Participation"!

We are thankful to all sponsors , participants and judges of the competition! We are grateful to LogicTronix for being Co-organizer of this FPGA Design Competition.

#FPGA #Competition #2020 #Nepal

Accelerate Machine Learning Application with FPGA over Cloud & Edge

Are you interested to accelerate your Machine Learning Task/Work?
Do you want to accelerate your ML task with better performance and power?
If then "Accelerating with FPGA" is the best "state of art" solution!
LogicTronix provide you turnkey solution on "Machine Learning Acceleration with FPGA over Edge or Cloud or in-Permise".

For more details: 
info@logictronix.com or please visit: www.LogicTronix.com

Machine Learning Flow on FPGA (Click on Image to Zoom)

International FPGA Design Competition 2019-Winner Announced

Digitronix Nepal and LogicTronix has organized the "International FPGA Design Competition 2019", the winner and runner-up of the competition has been announced at August 210, 2019. Here are the Winner and Runner-up of "International FPGA Design Competition-2019".
Winner: 32-bit Harvard Microprocessor, Team: Ahmad Khaled , Hassan Ibrahim , Ahmad Tolan , Ahmad Ashour, University/Affilation: Cairo University - Faculty of Engineering, Country: Egypt

Runner-up: Design and Implementation of a Frequency Hopping System based on FPGA, Team: Ahmed M. Alfadhel, University: Al-Furat Al-Awsat Technical University, Country: Iraq

We would like to Congratulate to all winners and all participating teams!
#International #FPGA #Design #Competition #2019

Here is the details of all teams participating on the Competition.

International FPGA Design Competition 2019

Along with "4th National FPGA Design Competition-2019", we are also hosting "Online Version" of separate "International FPGA Design Competition-2019". We already getting participant request for the "International FPGA Design Competition" from different Countries. Fill the registration form: bit.ly/FPGA_Competition_2019

For any queries: info@logictronix.com or digitronixnepali@gmail.com.

4th National FPGA Design Competition-2019

The timelines of 4th edition of FPGA Design Competition is released.The themes of competition is Open- enthusiast having any project on FPGA can get eligibility for the competition. Timelines [Revised] are

Registration : June 15- July 23, 2019
Pre-Project Demonstration : July 24-25, 2019
Final Demonstration & Prize Distribution: Saturday, July 27, 2019 (Shrawn 11,2076) Registration Form: https://forms.gle/XAyTSFA1FMo2Cgw48

Machine Learning with VCU1525 and Alveo

We just have released video tutorial session on "Machine Learning with VCU1525 and Alveo, High Performance Cloud Accelerator". In this session we are Implementing YoloV2 for Object Detection/Recognition on Cloud FPGA Accelerator.
#Nimbix #AWS #FPGA #VCU1525 #Alveo #Xilinx
https://www.youtube.com/watch?v=Pc-as5DMHJk. This implementation is done at Dec, 2018 by our team.