Tuesday, August 15, 2017

FPGA Board Access Assistance Program of Digitronix Nepal for Research/Academic Projects

Digitronix Nepal's "FPGA Board Access Assistance Program". Ary you interested to work or do project on Pynq or Zynq (Zybo/Zedboard) FPGA Boards? Currently we have provided Board Assistance Program to "Image Annotation with Zynq SoC" the Final Project of IOE Pulchowk Campus and "Face Recognition with Pynq FPGA with Computer Vision Algorithm" the Research Project at Digitronix Nepal with intern from IOE Thapathali Campus. They have get access and use Zynq/Pynq Boards on their project for specified project time. After project completes they will return those boards to Digitronix Nepal. If you required such FPGA Board Assistance then do send your Project Proposal/Draft at digitronixnepali@gmail.com or contact +977-9841078525. Digitronix Nepal's this plan cover following FPGA Boards Assistance in Nepal: ZedBoard FPGA, Zybo FPGA, Pynq FPGA.

Pynq FPGA Board
Zybo FPGA
Zedboard FPGA Board: a Zynq 7000 FPGA

Monday, July 31, 2017

FPGA Design with High Level Synthesis (HLS), Our Online Course at Udemy.com

High Level Synthesis is Hardware (FPGA) Design Approach which provides design flexibility to Hardware and Software Engineer. Designer/Engineer can script their algorithm on C/C++ with HLS Tool (as VIVADO HLS, one add in application package with VIVADO) and Convert the C/C++ project in to HDL (Verilog/VHDL and System C).So HLS Design Tools gives extensive library support on Video/Image Processing, Computer Vision and Mathematical Computation.

FPGA Design with High Level Synthesis at Udemy.com

Want to Learn more on HLS Design Methodology, Designing, Synthesizing, Simulating and Implementing (Exporting) HLS design then take the Udemy Course on : FPGA Design with VIVADO HLS, We have provided the Udemy.com's course coupon with this link so you can take this course at $10.
https://www.udemy.com/fpga-design-with-high-level-synthesis-vivado-hls/?couponCode=DIGITRONIXHLS10 or click here .

In the Course we have provided free preview session on VIVADO HLS Overview and Design Flow of HLS on FPGA Design. So Join the course and Get idea of HLS.

Sunday, July 23, 2017

Summary of Second All Nepal FPGA Design Competition July 15, 2017

Digitronix Nepal had Organized Second All Nepal FPGA Design Competition 2017 with Co-Organizers of Kathford Int'l College of Engineering and Management, National College of Engineering, Sagarmatha Engineering College and Kathmandu Engineering College.
The Second Edition of FPGA (Field Programmable Gate Array, a hardware design platform) has explore the different new ideas, research capability and development in Nepal. The Main Attraction of the Competition is AES (Advance Encryption Standard) Encryption of the data for communication, Face Recognition with PYNQ (Python+Zynq) FPGA, Image Annotation (recognition and labeling) with Zynq FPGA, OFDM (Orthogonal Frequency Division Multiplexing, an optimized FDM) implementation on FPGA, Voting Machine Design with FPGA. Judge and Visitors of the competition also heavily interested on Spectrum Analyzer with FPGA, Digital Clock with Spartan 3E, PS2 Keyboard and LCD interfacing with FPGA and LCD interfacing with FPGA.
This Edition of FPGA competition make a new direction on FPGA Research and Development in Nepal. Digitronix Nepal is partnering with National and International Companies/Organizations for manufacturing some of this feasible ideas and marketing on the global market.
Digitronix Nepal is hopeful that more and more stakeholders of the Hardware Design Ecosystem will join the “Hardware Research and Development Initiative in Nepal” for creating more and more opportunities for Nepalese Engineering professionals.

Friday, July 21, 2017

Tutorial on Configuring Flash PROM and SPI PROM with Spartan 3E

Digitronix Nepal has prepared Tutorial on :
  1. How to Create and Program Flash PROM XCf04s on Spartan 3E
     2. How to Program SPI PROM of Spartan 3E Tutorial by Rukesh Prajapati (Winner of Second All          Nepal FPGA Design Competition 2017) for Digitronix Nepal.
If you need this Tutorials on Spartan 3E FPGA then you can contact us at : digitronxinepali@gmail.com. This tutorial has been referenced from Xilinx UG230 for Spartan 3E.

Sunday, July 16, 2017

Second All Nepal FPGA Design Competition 2017 Completed Successfully

Lots of Congratulations to Khwopa Engineering College - KhEC
Team Rukesh Prajapati of "AES Encryption of data for secure wireless communication" for winning the Second All Nepal FPGA Design Competition 2017, Lots of Congratulations to TU, IOE, Thapathali Campus team Ashutosh Karna, Sushma Pokharel, Aayush Shah of "Voting Machine Design" for winning First Runner Up Prize and Lots of Congratulations to Nepal Engineering College team Rajan Kanu Baniya, Abhidan Jung Thapa of "Implementation of OFDM Transmitter in FPGA" for Winning Second Runner Up Prizes of the Competition.
We would like to congratulate all the Nine participant teams for competing on the National Level FPGA Competition.
We would like to thank Kathford International College of Engineering and ManagementNational College of Engineering (NCE)Sagarmatha Engineering College and Kathmandu Engineering College for Co-organizing/Sponsoring the competition.
We are thankful to our Chief Guest Dr. Surendra Shrestha (Reader, IOE Pulchowk Campus) for being with todays competition as Chief Guest.
We would like to thank our Jury Members Subodh Ghimire sir (Asst. Prof. KU, SOE), Dinesh Baniya Kshatri sir (DHOD, ECE , IOE Pulchowk) and Raju Shrestha sir (Lecturer, National College of Engineering - NCE)
We are thankful to Dr.मधुसुदन कायस्थ sir, Principal of Kathford International College of Engineering and Management and Saban Kumar KC Coordinator of Kathford Research & Development- R&D.
We are thankful to Shakya Deepesh Sir for inspiration and motivation for FPGA Research and Development in Nepal. Deepesh Sir's support and effort make this level on FPGA R & D in Nepal.

Friday, July 14, 2017

Thursday, June 8, 2017

Remember Digitronix Nepal For...

Digitronix Nepal is currently working on Hardware Design (Queue Management System, Temperature Display Systems,IoT Projects as Smart Home/Office Systems) based on Microcontrollers and Processors. We are also working on Real time Person Recognition based on FPGA. We can be remembered for 1. Electronic System Design and Manufacturing 2. Electro-Mechanical Systems 3. PCB Design (Single Layer/Multi Layer) based on Altium/OrCAD/Eagle CAD. 4. FPGA Design and Verification 5. FPGA based design implementation and testing. 6. Software based Systems (MIS, Desktop APP, Mobile APP, Websites) #DigitronixNepal #hardware #design #in #Nepal
Real Time Temperature Display and Logging System

Friday, June 2, 2017

VHDL Programming with Xilinx VIVADO and Zynq FPGA our Course at Udemy.com

Our Third Course on Udemy is now Live.The Course is of "VHDL Programming with Xilinx VIVADO and Zynq FPGA" , After completing this course enthusiast will able to get idea of VHDL Programming, Syntax, Design Methodology, Conditional Statements in VHDL, Simulation on VHDL with Testbench, Combinaitonal/Sequential Circuit Design in VHDL, Structural Design in VHDL and State Machine Design in VHDL. Hurry Up we are offering Discounted Coupons on the Course.
$10 Coupon Code Link of Udemy.com:https://www.udemy.com/vhdl-programming-with-xilinx-vivado-and-zynq-fpga/?couponCode=DIGITRONIX_VHDL10 



If you like to learn VHDL Programming with Xilinx ISE Design suit and Spartan/Nexys FPGA then here is $10 Coupon Code Link of Udemy:https://www.udemy.com/vhdl-programming-with-xilinx-ise-spartannexys-fpga/?couponCode=VHDL10

Thursday, June 1, 2017

Our 2nd Course at Udemy.com:Embedded System Design with Xilinx Zynq FPGA and VIVADO Design Suit

Our Another Online Course "Embedded System Design with Xilinx Zynq FPGA and VIVADO Design Suit" has been Published at Udemy.com. This Course consists Six Major Section with 5 hr on demand Video and course Cost $120 , which includes complete theoretical and practical session on Embedded Design with FPGA, VIVADO Design Methodology, Zynq Architecture, IP Design Methodology, Writing Software with SDK and Creating Bootable Applications targeted for Zynq FPGA (ZedBoard FPGA).For more details please visit the course link: 
https://www.udemy.com/embedded-system-design-with-xilinx-zynq-fpga-and-vivado/

Sunday, May 28, 2017

The Gleam of Electronic Hardware: Startup Story of Digitronix Nepal" on New Business Age Magazine Issue of May, 2017

"The Gleam of Electronic Hardware", New Business Age Magazine Issue of May; Page 84-85 Startup Scene. We are thankful to New Business Age Magazine team especially Nikeeta Gautam Miss for featuring our story on Startup Scene. We are Pushing our "Hardware Research and Design Initiative" to new edge, we believe to have a Silicon Street (as Silicon Valley ) in Nepal. So number of Innovative Ideas on Hardware Design and Development can foster and compete locally/globally. We are very much interested to be part of the Startup Ecosystem and recent development in Nepal on fostering/enhancing startup culture is very much inspiring and interesting. Initiative by STARTUPSNepalNepal Engineering Association , Biruwa Advisors , KUSOM and other Incubation/Venturing organization is inspiring. We hope in coming days there will have more Hardware Entrepreneurs as Software based Entrepreneurs in Nepal.
Here is the Online Link of the Article:The Gleam of Electronic Hardware, New Business Age Magazine.




Sunday, April 9, 2017

Real Time Temperature, Humidity Display and Logging System for Indoor or Outdoor Purpose" is Ready Now for Shipping

Our Product" Real Time Temperature, Humidity Display and Logging System for Indoor or Outdoor Purpose" is Ready Now. Here are some Product Features/Info
Features:
1. Real time,Temperature and Humidity Display on Seven Segment including one or two different places.
2. Logging (Information Save on 8GB SD Card) of temperature, humidity along with Real date/time in Microsoft Excel editable format (which is best for further analysis)
3. In system Display of Real time, temperature and logging information
4. It can be placed on any location on Office/Room, Size is (15x8 cm) same as of Attendance System.
Variants:
1. Different Size of Display based systems are available according to Client's requirement
2. System can be further Customized as Client's requirement
Cost: Cost will dependent on the features needed (Started from Few Hundred USD.)
Here are some Images of Product.
Real time temperature, humidity display and logging system by Digitronix Nepal

Interns Wanted at Digitronix Nepal for Different Application based Projects

Interns Wanted!!! 

Digitronix Nepal is interested to engage interns on following Application Specific projects.If you are really interested to join the internship (any one) and like to work on professional environment then contact us at: digitronixnepali@gmail.com
1. Smart Systems for Home/Office and Industries
2. Bead Threading Machine Design (Mechanical+Electronics)
3. FPGA based Traffic Sign Recognition system (Python+Machine Learning/Vision with OpenCV along with HDL)
5. Working with Latest State of Art FPGA's (Zedboard, Zybo and Pynq) for different application based projects (Programming in Verilog/VHDL/Tcl, Embedded C, Python).
4.To create and maintain an autonomous communication network for sensor packages, running on as low power as possible.The equipment's are 4 sensor packages, one MPLAB ICD 3 Microchip, One Zena Network Analyzer, 9V adapter.
5.Conception of system on chip multicore" (design and flow description in verilog)
6. Preparation of Online Course on Embedded System Design with Zynq FPGA and Xilinx VIVADO Design Suit.
7.A Facial Expression Classification System Integrating Canny, Principal Component Analysis and Artificial Neural Network with MATLAB/Simulink.
For more detail about Digitronix Nepal and Internship Programs please mail us
, We also have forum/Facebook Group for Projects;  with more project details : Digitronix Nepal Forum


Thursday, March 30, 2017

Digitronix Nepal's Online Course on "Verilog HDL Programming for Beginners with Xilinx ISE Design Suit" is now Live at Udemy.com


We are glad to share that Digitronix Nepal's Online Course on "Verilog HDL Programming for Beginners with Xilinx ISE Design Suit" has been Published and Live at Udemy.com (Udemy is US based Online Learning and Teaching Marketplace). This is the first ever Hardware based course from Nepal has been published on Online Course Site.We are preparing more courses on FPGA/ASIC/VLSI with VHDL/Verilog/Tcl which will published soon on Online Course Sites. This Course Cost Just $85 and student will get certification from Udemy.com.
This Course can be reached at: https://www.udemy.com/course/1138718

Monday, January 30, 2017

Digitronix Nepal: FPGA Tutorial Series on YouTube

Digitronix Nepal has Updated own YouTube Channel with more new Video on ISE Design Suit, Spartan 3E, Zybo FPGA, Pynq FPGA and ZedBoard FPGA. We Currently have more than 30 Tutorials on FPGA Design using ISE Design Suit & Vivado Design Suit from Xilinx.Now, We have more than 10 Turorial Session on ZedBoard, similar no of Zybo Tutorials (including how to create IP in HDL and HLS, Program FPGA in VHDL/Verilog) and we also have ISE and Spartan FPGA Tutorials on: Basic Logic Gate Design, Full Adder Design Structurally and Finite State Machine based Design in VHDL.You will get complete idea of How to Write VHDL Programs ,Create Bitstream and then Configure FPGA.

Along with this tutorials we also have releases our VHDL/Verilog and Tcl Reference Guides for Enthusiasts. We believe that enthusiasts can get huge benifit from this resources and can do/work on Projects based on FPGA and Microcontrollers. 

We also have different Internship offerings on FPGA research and development and Internet Of Things. We have more than 20 Tutorial series on different Microcontrollers to.

or go to ISE Design Suit Tutorial Playlist:



Tutorials on ZedBoard , Zybo, Pynq, Spartan 3E FPGA with ISE and VIVADO Design Suit

Tutorial for Beginners on Spartan 3E with VHDL and ISE Design Suit.
Some Videos are also available here for watching:

How to Create IP in VIVADO HLS: Watch

Thursday, January 19, 2017

Digitronix Nepal Projects on Zedboard along with Pynq ,Zybo & Spartan 3E

Digitronix Nepal has prepared & published the Video Tutorial series on ZedBoard FPGA, Spartan 3E FPGA, Nexys 3 FPGA, Zybo FPGA and Pynq FPGA previously at YouTube: https://www.youtube.com/c/digitronixnepal  and http://www.digitronixnepal.com/
Digitronix Nepal has prepared lots of Tutorial Series on FPGA, Currently in our YouTube Channel we have 8 Tutorials on Zedboard FPGA (including how to create IP in HDL and HLS, Program FPGA in VHDL/Verilog), 6 Tutorials on Zybo FPGA , 5 Tutorials on Spartan 3E and Different Projects of National FPGA Design Contest. We are syncing/uploading more tutorials on our Youtube Channel. Keep Streaming on our Youtube Channel!!! Along with this tutorials we also have releases our VHDL/Verilog and Tcl Reference Guides for Enthusiasts. We believe that enthusiasts can get huge benifit from this resources and can do/work on Projects based on FPGA and Microcontrollers. We also have different Internship offerings on FPGA research and development and Internet Of Things. We have more than 20 Tutorial series on different Microcontrollers to.
 Watch the video:of Zedboard Tutorial on Creating Custom Verilog IP of PWM in Vivado by Digitronix Nepal 
Projects Plan on ZedBoard:
1. Implementing a Image Processing System in OpenCV Framework
2. Designing a Traffic Sign Identification system for ADAS Application
3. Ethernet Firewall Design and Implementation on Zedboard
4. SDN and SDR Implementation 
5. Encryption Algorithm implementation on Zedboard
6. Embedding Custom Linux for Real Time Applications.
             We will welcome Project Ideas/Plan/Proposal from the Enthusiast and Clients.

Friday, January 6, 2017

Interaction Program on FPGA Design through Xilinx University Program (XUP)

Interaction Program on "FPGA Design through Xilinx University Program (XUP)" has been successfully completed which was Organized by Kathford Research & Development- R&D and Digitronix Nepal on Jan 6, 2017 at Kathford International College of Engineering and Management . We are thankful to Deepesh Man Shakya Sir for presenting insights on Global Trend on FPGA Design and It's implication in Nepal. We are especially thankful to Dr. Madhusudan Kayastha (मधुसुदन कायस्थ)Sir, Principal of KICEM for supporting on this initiation. We are thankful to Department Heads ,Professors/Lecturers and Students of different engineering colleges of Nepal.

Interaction Program on FPGA Design Poster
Principal of Kathford, Dr. Madhusudan Kayastha providing Token of Love to Guest Speaker of Program ,Deepesh Man Shakya (Xilinx Inc, Ireland).
Principal of Kathford, Dr. Madhusudan Kayastha providing Token of Love to Guest Speaker of Program ,Deepesh Man Shakya (Xilinx Inc, Ireland).

Participatants of the Interaction Program and Demonstration of FPGA Projects on Spartan 3e, Zybo and Pynq FPGA by Samundra K. Thapa and Ashutosh Karna.
The Resolution of the Interaction Program on FPGA Design through Xilinx University Program (XUP) can be found here: Resolution of interaction Program on FPGA and XUP